Oleg Zabluda's blog
Sunday, April 02, 2017
 
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the CPU complex of the Drive PX 2 board is as follows: There are 2 Denver2 cores present plus 4x Cortex A57 cores. The architecture used is ARM v8 64 bit. The CPU Complex will have upto 8 GB of LPDDR4 memory (UMA) with up to 50 GB/s bandwidth. Nvidia’s 5th generation architecture, aka Pascal, features custom acceleration for deep learning and the discrete GPUs present will have up to 80 GB/s of bandwidth.
[...]
Each CPU complex will have access to its own integrated Pascal Cores (as well as a dedicated Pascal GPU over PCIe) and will be connected by a 1 Gb Ethernet connection. The discrete Pascal cores will have up to 4GB of GDDR5 memory (each) and will feature approximately 80 GB/s of bandwidth – which tells us that we are probably looking at low end (or custom) cores around the GP106 spectrum. They use a 128-bit interface that connects to four GDDR5 memory chips clocked at 1.25 GHz. The clock can go as high as 1.5 GHz for a total of 96 GB/s.
[...]
The Pascal cores used on the Drive PX 2 has a specialized instruction set that is designed to accelerate DNN performance on the go . The interface itself (of the PX 2 board) supports an IO of 70 Gigabits per second. Interestingly, Nvidia has put a lot of thought on redundancy and mission critical system safety. An ASIL-D safety micro controller is also present on the board itself. Not only that, but the hardware is AutoSAR compliant, and designed from the ground up to allow devs to take full advantage of the resources on the board.
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http://wccftech.com/nvidia-drive-px2-pascal-gtc-2016/
http://wccftech.com/nvidia-drive-px2-pascal-gtc-2016/

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